1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an improved process for planarizing trench isolation regions of varying geometry.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are interconnected by a conductor which extends over a dielectric which separates or "isolates" those devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS process involves oxidizing field regions between devices. The oxide grown in field regions are termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beak structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant oftentimes redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily affects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the "shallow trench process." Despite advances made to decrease bird's-beak, channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep submicron MOS technologies. The shallow trench process is better suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.3 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width.
While the trench isolation process has many advantages over LOCOS, it cannot in all instances achieve complete global planarization across the entire semiconductor topography. The upper surface of fill dielectric in large isolation areas are at lower elevation levels than the upper surface of the fill dielectric in small isolation areas. Further, manipulation of the fill dielectric surface is needed to provide an elevationally uniform fill dielectric surface across both large isolation areas (e.g., greater than 2.0 microns per side) and small isolation areas (e.g., less than 1.0 micron per side). The trench process presents many additional problems besides that of local planarization. First, conventional chemical vapor deposition (CVD) processes exhibit a tendency to form cusps and/or voids at the midline between closely spaced active areas, hereinafter termed "silicon mesas." These voids can lead to reliability problems and inadequate isolation performance. Second, conventional planarization techniques used to remove the fill dielectric from the upper surface of silicon mesas may over etch the fill dielectric in the isolation areas relative to the silicon mesas. An over etched fill surface which is elevationally lower than an adjacent active area silicon mesa causes the mesa sidewall and corner to be partially exposed. Any exposure at the silicon mesa corner or sidewall causes inappropriate fringing field effects and/or parasitic sidewall conduction. It is therefore important when choosing a planarization method, that the method not expose the silicon mesa corner or sidewall. Lastly, it is important to protect the silicon mesa upper surface during the fill procedure and subsequently during planarization. The silicon mesa surface must be left in pristine condition so as to allow formation of a high quality gate or tunnel oxide thereon. Local thinning of the resulting gate and/or tunnel oxide cannot be tolerated in high density integrated circuits employing short channels.